1. Field of the Invention
The present invention relates to an optical receiver and, more particularly, to a differential optical receiver fabricated in ultra-thin silicon on sapphire CMOS permitting low-power, high-speed operation useful for communication between CMOS chips or platforms and with vertical cavity surface emitting laser (VCSEL) array technology.
2. Description of the Related Art
Processors fabricated in deep sub-micron CMOS (complimentary metal oxide semiconductor) have rapidly advanced to where internal data is processed at gigahertz rates. While computation proceeds at gigahertz rates internally, external wiring and buses have become the bottleneck of high performance systems. In order to maintain high bandwidth operation of multi-chip systems, optical signals are increasingly used as the media for parallel inter-chip communication. With the advent of vertical cavity surface emitting lasers (VCSELs), it is now possible to increase data transmission capacity between CMOS chips by using arrays of high bandwidth optical sources and detectors. For practical purposes, small footprint, low-power receiver arrays are highly desirable in these system.
Such optical communication channels require conversion of optical signals into electrical signals and vice-versa. High speed performance of optical interconnects is typically limited by the high speed performance of optical receivers. While many optical detectors (PIN diodes and MSMs) have bandwidths above 20 GHz, photocurrent may be as low as 10 xcexcA for incident laser input, as noted by Gupta in xe2x80x9cHandbook of Photonics,xe2x80x9d CRC Press, 1997, the disclosure of which is incorporated herein by reference in its entirety. Most designers approach this problem by using limited bandwidth and high gain, or by supplying additional power. Limited bandwidth approaches are described by Ingels et al. in xe2x80x9cA CMOS 18 thz-ohm 240 mb/s transimpedance amplifier and 155 mb/s led-driver for low cost optical fiber links,xe2x80x9d IEEE J. Solid State Circuits, 29(12):1552+, December 1994, and by Phang et al. in xe2x80x9cA CMOS optical preamplifier for wireless infrared communications,xe2x80x9d IEEE Trans. Circuits and Systems, 46(7):852-859, July 1999, the disclosures of which are incorporated herein by reference in their entireties. Commercial Anadigics receiver circuits require 0.1 W at 2 GHz bandwidth, as reported by Jayakumar et al. in xe2x80x9c3-v MSM TIA for gigabit Ethernet,xe2x80x9d Journal of Solid-State Circuits, 35(9), September 2000, the disclosure of which is incorporated herein by reference in its entirety. Another solution has been to design receiver circuits directly on optical detector substrates. These designs are limited in their practical use, since they are not supported by the silicon design and fabrication infrastructure.
A 0.25 xcexcm CMOS design operating at 1.5 Gbit/s consuming 26 mW is disclosed by Woodward et al. in xe2x80x9cLow-power, small-footprint gigabit Ethernet-compatible optical receiver circuit in 0.25 xcexcm CMOS,xe2x80x9d Electronics Letters, 36(17):1489+, August 2000, the disclosure of which is incorporated herein by reference in its entirety. A number of other designs consuming over 100 mW per channel have been reported, including those described in the aforementioned paper by Phang et al. and by Ingels et al. in xe2x80x9cA 1xe2x88x92gb/s, 0.7xe2x88x92xcexcm CMOS optical receiver with full rail-to-rail output swing,xe2x80x9d IEEE J. Solid State Circuits, 34(7):971+, July 1999, the disclosure of which is incorporated herein by reference in its entirety. However, high-speed optical detector devices which consume less power (e.g., under 10 mW) have not yet been developed. Accordingly, there remains a need for a fast, low-power CMOS-based optical receiver to facilitate commercial development of optical detector arrays for use in high-speed CMOS electronics.
Therefore, in light of the above, and for other reasons that become apparent when the invention is fully described, an object of the present invention is to provide a high-speed, low-power optical receiver.
A further object of the present invention is to provide an optical receiver suitable for forming optical receiver arrays.
Yet a further object of the present invention is to provide an optical receiver compatible with high-speed CMOS circuits.
A still further object of the present invention is to provide an optical receiver which allows for the production of stacked integrated circuit devices with optical vias.
Another object of the present invention is to provide a fully differential optical receiver to reject interference, electrical offsets, and power supply noise.
Yet another object of the present invention is to minimize the footprint of an integrated circuit optical receiver.
The aforesaid objects are achieved individually and in combination, and it is not intended that the present invention be construed as requiring two or more of the objects to be combined unless expressly required by the claims attached hereto.
In accordance with the present invention, a fully differential optical receiver circuit is designed for low-power, high-bandwidth, optical communication between CMOS chips or platforms, such as in stacked, multi-chip CMOS architectures employing optical inter-chip communication. In an exemplary embodiment, a linear array of CMOS optical receivers formed on a single chip operates in parallel from a common power supply. The receiver chip is fabricated in an Ultra-Thin Silicon on Sapphire (Utsi) CMOS 0.5 xcexcm process which enables the design of high speed circuits with low power consumption and no substrate cross-talk. Each optical receiver channel in the array comprises a multi-stage differential amplifier circuit comprising a first differential transimpedance stage followed by a plurality of differential feed-forward, high-bandwidth gain stages and a final, differential-to-single-ended converter output stage. The inputs of the transimpedance stage receive a differential input signal from metal-semiconductor-metal (MSM) or PIN diode photo-detectors. In accordance with another aspect of the present invention, a novel cross-coupled transimpedance stage is preferably used as the input stage of the optical receiver when capacitive loads from the optical detectors can be made small (e.g., with MSMs), since high gain can be achieved in this architecture without large input gates. Each channel of the array consumes 5 mW of power from a 3.3 V supply with a transimpedance gain of 25 kxcexa9, and may operate up to 1 Gbit/s with 0.5 pF MSM photo-detectors. This is the fastest CMOS receiver known to the inventors that consumes under 10 mW.
An important aspect of the present invention which is facilitated by the use of silicon on insulator technology is the use of varied or different threshold transistors within each differential amplifier stage. With lower gate thresholds, certain transistors serve as current sources, providing more current per unit size, reducing the overall size of the footprint of the circuit, and improving the bandwidth by decreasing the parasitic capacitance. By contrast, the input switching transistors of each amplifier stage have higher thresholds.
As a differential receiver, the circuit effectively rejects electrical interference, power supply noise and voltage offsets. These characteristics make the optical receiver cell of the present invention ideal for use in a multidimensional array of optical interconnects. The advent of ultra-thin silicon on sapphire CMOS enables the optical receiver of the present invention to overcome many of the power and speed constraints which limit bulk CMOS receiver performance. Substrate isolation in Silicon on Sapphire (SOS) CMOS is used in the design of the optical receivers to reduce cross-talk, noise, and instability that are characteristic of bulk CMOS receiver designs. Due to the absence of significant parasitic capacitance, the sapphire substrate permits a greater number of amplifier stages to be formed in the optical receiver, thereby yielding greater receiver gain.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following definitions, descriptions and descriptive figures of specific embodiments thereof wherein like reference numerals in the various figures are utilized to designate like components. While these descriptions go into specific details of the invention, it should be understood that variations may and do exist and would be apparent to those skilled in the art based on the descriptions herein.